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HS-82C08RH
February 1996
Radiation Hardened 8-Bit Bus Transceiver
Functional Diagram
Features
* Devices QML Qualified in Accordance With MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Intersil' QM Plan * Radiation Hardened - Total Dose 1 x 105 RAD (Si) - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s * Bidirectional Three-State Input/Outputs * Low Propagation Delay Time * Low Power Consumption * Single Power Supply +5V * Electrically Equivalent to Sandia SA2997 * Military Temperature Range -55oC to +125oC
A0
B0
A1 A2 A3 PORT A4 A A5 A6 A7
B1 B2 B3 B4 PORT B B5 B6 B7
T/R
Description
The Intersil HS-82C08RH is a radiation-hardened octal bus transceiver with three-state outputs. It is manufactured using a self-aligned, junction isolated CMOS process and is designed for use with the HS-80C08RH radiation-hardened microprocessor. The HS-82C08RH allows asynchronous two-way communication between data buses. The direction of data flow is determined by the logic level on the transmit/ receive (T/R) input. A logic high on the T/R input specifies data flow from Port A to Port B of the device. Conversely, a logic low on the T/R input specifies data flow from Port B to Port A. The Output Enable input disables both ports by placing them in the high impedance state. The HS-82C08RH is ideally suited for a wide variety of buffering applications in radiation-hardened microcomputer systems.
OE
TRUTH TABLE INPUTS OUTPUT ENABLE 0 0 1 X = Don't Care TRANSMIT /RECEIVE 0 1 X OPERATION
PORT A Out In High Z
PORT B In Out High Z
Ordering Information
PART NUMBER 5962R9571401QRC 5962R9571401QXC 5962R9571401VRC 5962R9571401VXC HS1-82C08RH/SAMPLE HS9-82C08RH/SAMPLE TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC SCREENING LEVEL MIL-PRF-38535 Level Q MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level V SAMPLE SAMPLE PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack
-55oC to +125oC -55oC to +125oC
+25oC +25oC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518057 3040.2
HS-82C08RH Pinouts
20 LEAD CERAMIC DUAL-IN-LINE METAL-SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T20 TOP VIEW
A0 A1 A2 A3 A4 A5 A6 A7 OE 1 2 3 4 5 6 7 8 9 20 VDD 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 T/R
20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F20 TOP VIEW
A0 A1 A2 A3 A4 A5 A6 A7 OE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD B0 B1 B2 B3 B4 B5 B6 B7 T/R
GND 10
PIN A0-A7 B0-B7
DESCRIPTION Local Bus Data I/O Pins System Bus Data I/O Pins
PIN T/R OE
DESCRIPTION Transmit/Receive Input Active Low Output Enable
Logic Diagram
A0 1 TSB TSB A1 2 TSB TSB A2 3 TSB TSB A3 4 TSB TSB 5 TSB TSB A5 OE 9 6 B ENABLE A6 T/R11 A7 8 7 A ENABLE TSB TSB TSB TSB 12 B7 TSB TSB 13 B6 14 B5 15 16 B3 17 B2 18 B1 19 B0
A4
B4
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-state condition. A transient drive current of 1.5mA at VDD/2 0.5V for 10ns is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions.
Spec Number 2
518057
Specifications HS-82C08RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC 20 Lead SBDIP Package. . . . . . . . . . . . . 71oC/W 17oC/W 20 Lead Ceramic Flatpack Package . . . . 85oC/W 25oC/W Maximum Package Power Dissipation at +125oC Ambient 20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.70W 20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . 0.59W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: 20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . .14.1mW/C 20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . . 11.8mW/C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +1V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VDD -1V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS All Devices Guaranteed at Worst Case Limits and Conditions. GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 7, 8A, 8B LIMITS TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC 4.25 1.0 0.5 100 MIN -1.0 MAX UNITS A A V V A -
PARAMETER Input Leakage Current
SYMBOL IIL IIH
CONDITIONS VDD = 5.25V, VIN = VDD Pin Under Test = 0V VDD = 5.25V, VIN = 0V Pin Under Test = 5.25V VDD = 4.75V, IOH = -2.0mA VDD = 5.25V, IOL = 2.0mA VDD = 5.25V, VIN = GND VDD = 4.75V to 5.25V VIH = VDD -1.0V, VIL = 1.0V
High Level Output Voltage Low Level Output Voltage Static Current Functional Test
VOH VOL SIDD FT
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX UNITS
PARAMETER PORT DATA/MODE SPECIFICATIONS Propagation Delay to Logical "1" from Port A, B to Port B, A Propagation Delay to Logical "0" from Port A, B to Port B, A Propagation Delay from High-Impedance to Logical "1" from T/R to Port Propagation Delay from High-Impedance to Logical "0" from T/R to Port Propagation Delay from High-Impedance to Logical "1" from OE to Port Propagation Delay from High-Impedance to Logical "0" from OE to Port
SYMBOL
TPDLH TPDHL TPRTH TPRTL TPZH TPZL
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
-
65 80 75 130 70 130
ns ns ns ns ns ns
Spec Number 3
518057
Specifications HS-82C08RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE) CONDITIONS VDD = Open, f = 1MHz All Measurements Referenced to GND. LIMITS TEMPERATURE +25oC MIN MAX 10 UNITS pF
PARAMETER In/Out Capacitance
SYMBOL CI/O
TRANSMIT/RECEIVE MODE SPECIFICATIONS (AC Parameters) Propagation Delay from Logical "1" to High-Impedance from T/R to Port Propagation Delay from Logical "0" to High-Impedance from T/R to Port Propagation Delay from Logical "1" to High-Impedance from OE to Port Propagation Delay from Logical "0" to High-Impedance from OE to Port NOTE: 1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which could affect these characteristics. TPHZTR TPLZTR TPHZ TPLZ +25oC +25oC +25oC +25oC 35 35 35 35 ns ns ns ns
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC; In Accordance With SMD)
Switching Time Waveforms
TR INPUT AN OR BN VDD 0V VDD 0.5VDD 0V 0.5VDD TR = TF 20ns 10% to 90% 0.5VDD tPLH 0.5VDD tPHL TF DEVICE UNDER TEST
TEST POINTS CL (NOTE)
OUTPUT BN OR AN
NOTE: CL includes stray and jig capacitance. FIGURE 2. AC TESTING LOAD CIRCUIT
FIGURE 1. PORT TO PORT
VDD INPUT OE 0V PORT VOH OUTPUT tPHZ tPLZ PORT VOL OUTPUT 0.5VDD
TR 0.1VDD
TR = TF 20ns 10% to 90%
TF 0.5VDD
tPZH 0.5VDD 0V
VDD 0.5VDD tPZL 0.1VDD
FIGURE 3. OE TO HIGH-IMPEDANCE, OE TO PORT OUTPUT
Spec Number 4
518057
HS-82C08RH Metallization Topology
DIE DIMENSIONS: 76.0 mils x 89.4 mils x 14 mils 1 mil METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA
Metallization Mask Layout
HS-82C08RH
(20) VDD
A1 (2)
(19) B0
(1) A0
(18) B1
A2 (3)
(17) B2
A3 (4)
(16) B3
A4 (5)
(15) B4
A5 (6)
(14) B5
A6 (7)
(13) B6
A7 (8) GND (10) T/R (9) OE (9)
(12) B7
Spec Number 5
518057
HS-82C08RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Spec Number 6

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